Hardware Acceleration of Algorithm

Sponsored by: NovTech Inc

 

Abstract
This project is about developing a hardware solution on a field-programmable gate array (FPGA) that performs the execution of an algorithm (in this case: Normalized Correlation) faster than an equivalent, software implemented version. The solution takes advantage of the FPGA’s parallel computing capabilities to calculate correlation values based on image input. An equivalent software solution is also built to demonstrate the performance benefits of the hardware solution. Both solutions send their correlation values and calculation times over to an Android App to be displayed. Community Benefit: A Normalized Correlation Algorithm, specifically designed to take advantage of the FPGA’s parallelism capabilities, allows the algorithm to run faster and more efficiently on an FPGA for use in applications such as motion-tracking, facial recognition, or medical imaging.

Team Members

Sauvens Fleurinord
Jared Hermans
Renison Joseph
Michael Sarubbe
Sergio Villanueva